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?2001 silicon storage technology, inc. s71209-00-000 9/01 557 1 the sst logo and superflash are registered trademarks of silicon storage technology, inc. mpf and combomemory are trademarks of silicon storage technology, inc. these specifications are subject to change without notice. preliminary specifications features: ? mpf + sram combomemory ? sst32hf201: 128k x16 flash + 64k x16 sram ? sst32hf202: 128k x16 flash + 128k x16 sram ? sst32hf401: 256k x16 flash + 64k x16 sram ? sst32hf402: 256k x16 flash + 128k x16 sram single 2.7-3.3v read and write operations concurrent operation ? read from or write to sram while erase/program flash superior reliability ? endurance: 100,000 cycles (typical) ? greater than 100 years data retention low power consumption: ? active current: 15 ma (typical) for flash or sram read ? standby current: 20 a (typical) flexible erase capability ? uniform 2 kword sectors ? uniform 32 kword size blocks fast read access times: ? flash: 70 and 90 ns ? sram: 70 and 90 ns latched address and data for flash flash fast erase and word-program: ? sector-erase time: 18 ms (typical) ? block-erase time: 18 ms (typical) ? chip-erase time: 70 ms (typical) ? word-program time: 14 s (typical) ? chip rewrite time: sst32hf201/202: 2 seconds (typical) sst32hf401/402: 4 seconds (typical) flash automatic erase and program timing ? internal v pp generation flash end-of-write detection ? toggle bit ? data# polling cmos i/o compatibility jedec standard command set conforms to flash pinout package available ? 48-ball lfbga (6mm x 8mm) product description the sst32hf20x/40x combomemory devices integrate a 128k x16 or 256k x16 cmos flash memory bank with a 64k x16 or 128k x16 cmos sram memory bank in a multi-chip package (mcp), manufactured with sst?s pro- prietary, high performance superflash technology. featuring high performance word-program, the flash memory bank provides a maximum word-program time of 14 sec. the entire flash memory bank can be erased and programmed word-by-word in typically 2 seconds for the sst32hf201/202 and 4 seconds for the sst32hf401/ 402, when using interface features such as toggle bit or data# polling to indicate the completion of program opera- tion. to protect against inadvertent flash write, the sst32hf20x/40x devices contain on-chip hardware and software data protection schemes.the sst32hf20x/40x devices offer a guaranteed endurance of 10,000 cycles. data retention is rated at greater than 100 years. the sst32hf20x/40x devices consist of two independent memory banks with respective bank enable signals. the flash and sram memory banks are superimposed in the same memory address space. both memory banks share common address lines, data lines, we# and oe#. the memory bank selection is done by memory bank enable signals. the sram bank enable signal, bes# selects the sram bank. the flash memory bank enable signal, bef# selects the flash memory bank. the we# signal has to be used with software data protection (sdp) command sequence when controlling the erase and program opera- tions in the flash memory bank. the sdp command sequence protects the data stored in the flash memory bank from accidental alteration. the sst32hf20x/40x provide the added functionality of being able to simultaneously read from or write to the sram bank while erasing or programming in the flash memory bank. the sram memory bank can be read or written while the flash memory bank performs sector- erase, bank-erase, or word-program concurrently. all flash memory erase and program operations will automati- cally latch the input address and data signals and complete the operation in background without further input stimulus requirement. once the internally controlled erase or pro- gram cycle in the flash bank has commenced, the sram bank can be accessed for read or write. the sst32hf20x/40x devices are suited for applications that use both flash memory and sram memory to store code or data. for systems requiring low power and small form factor, the sst32hf20x/40x devices significantly improve performance and reliability, while lowering power multi-purpose flash (mpf) + sram combomemory sst32hf201 / sst32hf202 / sst32hf401 / sst32hf402 sst32hf201 / 202 / 401 / 4022mb flash + 1mb sram, 2mb flash + 2mb sram, 4mb flash + 1mb sram, 4mb flash + 2mb sram (x16) mcp combomemories
2 preliminary specifications multi-purpose flash (mpf) + sram combomemory sst32hf201 / sst32hf202 / sst32hf401 / sst32hf402 ?2001 silicon storage technology, inc. s71209-00-000 9/01 557 consumption, when compared with multiple chip solutions. the sst32hf20x/40x inherently use less energy during erase and program than alternative flash technologies. the total energy consumed is a function of the applied voltage, current, and time of application. since for any given voltage range, the superflash technology uses less current to pro- gram and has a shorter erase time, the total energy con- sumed during any erase or program operation is less than alternative flash technologies. the superflash technology provides fixed erase and pro- gram times, independent of the number of erase/program cycles that have occurred. t herefore the system software or hardware does not have to be modified or de-rated as is necessary with alternative flash technologies, whose erase and program times increase with accumulated erase/program cycles. device operation the combomemory uses bes# and bef# to control oper- ation of either the sram or the flash memory bank. when bes# is low, the sram bank is activated for read and write operation. when bef# is low the flash bank is acti- vated for read, program or erase operation. bes# and bef# cannot be at low level at the same time. if bes# and bef# are both asserted to low level bus contention will result and the device may suffer permanent damage. all address, data, and control lines are shared by sram bank and flash bank which minimizes power consumption and loading. the device goes into standby when both bank enables are high. sram operation with bes# low and bef# high, the sst32hf201/401 operate as 64k x16 cmos sram, and the sst32hf202/ 402 operates as 128k x16 cmos sram, with fully static operation requiring no external clocks or timing strobes. the sst32hf201/401 sram is mapped into the first 64 kword address space of the device, and the sst32hf202/402 sram is mapped into the first 128 kword address space. when bes# and bef# are high, both memory banks are deselected and the device enters standby mode. read and write cycle times are equal. the control signals ubs# and lbs# provide access to the upper data byte and lower data byte. see table 3 for sram read and write data byte control modes of operation. sram read the sram read operation of the sst32hf20x/40x is controlled by oe# and bes#, both have to be low with we# high for the system to obtain data from the outputs. bes# is used for sram bank selection. oe# is the output control and is used to gate data from the output pins. the data bus is in high impedance state when oe# is high. see figure 2 for the read cycle timing diagram. sram write the sram write operation of the sst32hf20x/40x is controlled by we# and bes#, both have to be low for the system to write to the sram. during the word-write oper- ation, the addresses and data are referenced to the rising edge of either bes# or we#, whichever occurs first. the write time is measured from the last falling edge to the first rising edge of bes# or we#. see figures 3 and 4 for the write cycle timing diagrams. flash operation with bef# active, the sst32hf201/202 operate as 128k x16 flash memory and the sst32hf401/402 operates as 256k x16 flash memory. the flash memory bank is read using the common address lines, data lines, we# and oe#. erase and program operations are initiated with the jedec standard sdp command sequences. address and data are latched during the sdp commands and during the internally timed erase and program operations. flash read the read operation of the sst32hf20x/40x devices is controlled by bef# and oe#. both have to be low, with we# high, for the system to obtain data from the outputs. bef# is used for flash memory bank selection. when bef# and bes# are high, both banks are deselected and only standby power is consumed. oe# is the output con- trol and is used to gate data from the output pins. the data bus is in high impedance state when oe# is high. refer to figure 5 for further details. flash erase/program operation sdp commands are used to initiate the flash memory bank program and erase operations of the sst32hf20x/40x. sdp commands are loaded to the flash memory bank using standard microprocessor write sequences. a com- mand is loaded by asserting we# low while keeping bef# low and oe# high. the address is latched on the falling edge of we# or bef#, whichever occurs last. the data is latched on the rising edge of we# or bef#, whichever occurs first. flash word-program operation the flash memory bank of the sst32hf20x/40x devices is programmed on a word-by-word basis. before program operations, the memory must be erased first. the program
preliminary specifications multi-purpose flash (mpf) + sram combomemory sst32hf201 / sst32hf202 / sst32hf401 / sst32hf402 3 ?2001 silicon storage technology, inc. s71209-00-000 9/01 557 operation consists of three steps. the first step is the three- byte load sequence for software data protection. the sec- ond step is to load word address and word data. during the word-program operation, the addresses are latched on the falling edge of either bef# or we#, whichever occurs last. the data is latched on the rising edge of either bef# or we#, whichever occurs first. the third step is the internal program operation which is initiated after the rising edge of the fourth we# or bef#, whichever occurs first. the pro- gram operation, once initiated, will be completed, within 20 s. see figures 6 and 7 for we# and bef# controlled pro- gram operation timing diagrams and figure 17 for flow- charts. during the program operation, the only valid flash read operations are data# polling and toggle bit. during the internal program operation, the host is free to perform additional tasks. any sdp commands loaded during the internal program operation will be ignored. flash sector/block-erase operation the flash sector/block-erase operation allows the system to erase the device on a sector-by-sector (or block-by- block) basis. the sst32hf20x/40x offer both sector- erase and block-erase mode. the sector architecture is based on uniform sector size of 2 kword. the block-erase mode is based on uniform block size of 32 kword. the sector-erase operation is initiated by executing a six-byte command sequence with sector-erase command (30h) and sector address (sa) in the last bus cycle. the address lines a 16 -a 11 , for sst32hf201/202, and a 17 -a 11 , for sst32hf401/402, are used to determine the sector address. the block-erase operation is initiated by execut- ing a six-byte command sequence with block-erase com- mand (50h) and block address (ba) in the last bus cycle. the address lines a 16 -a 15 , for sst32hf201/202, and a 17 - a 15 , for sst32hf401/402, are used to determine the block address. the sector or block address is latched on the fall- ing edge of the sixth we# pulse, while the command (30h or 50h) is latched on the rising edge of the sixth we# pulse. the internal erase operation begins after the sixth we# pulse. the end-of-erase operation can be deter- mined using either data# polling or toggle bit methods. see figures 11 and 12 for timing waveforms. any com- mands issued during the sector- or block-erase operation are ignored. flash chip-erase operation the sst32hf20x/40x provide a chip-erase operation, which allows the user to erase the entire memory array to the ?1? state. this is useful when the entire device must be quickly erased. the chip-erase operation is initiated by executing a six- byte command sequence with chip-erase command (10h) at address 5555h in the last byte sequence. the erase operation begins with the rising edge of the sixth we# or ce#, whichever occurs first. during the erase operation, the only valid read is toggle bit or data# polling. see table 4 for the command sequence, figure 9 for timing diagram, and figure 20 for the flowchart. any commands issued dur- ing the chip-erase operation are ignored. write operation status detection the sst32hf20x/40x provide two software means to detect the completion of a write (program or erase) cycle, in order to optimize the system write cycle time. the soft- ware detection includes two status bits: data# polling (dq 7 ) and toggle bit (dq 6 ). the end-of-write detection mode is enabled after the rising edge of we#, which ini- tiates the internal program or erase operation. the actual completion of the nonvolatile write is asynchro- nous with the system; therefore, either a data# polling or toggle bit read may be simultaneous with the completion of the write cycle. if this occurs, the system may possibly get an erroneous result, i.e., valid data may appear to con- flict with either dq 7 or dq 6. in order to prevent spurious rejection, if an erroneous result occurs, the software routine should include a loop to read the accessed location an additional two (2) times. if both reads are valid, then the device has completed the write cycle, otherwise the rejec- tion is valid. flash data# polling (dq 7 ) when the sst32hf20x/40x flash memory banks are in the internal program operation, any attempt to read dq 7 will produce the complement of the true data. once the program operation is completed, dq 7 will produce true data. note that even though dq 7 may have valid data immediately following the completion of an internal write operation, the remaining data outputs may still be invalid: valid data on the entire data bus will appear in subsequent successive read cycles, after an interval of 1 s. during internal erase operation, any attempt to read dq 7 will pro- duce a ?0?. once the internal erase operation is completed, dq 7 will produce a ?1?. the data# polling is valid after the rising edge of the fourth we# (or bef#) pulse for program operation. for sector- or block-erase, the data# polling is valid after the rising edge of the sixth we# (or bef#) pulse. see figure 8 for data# polling timing diagram and figure 18 for a flowchart.
4 preliminary specifications multi-purpose flash (mpf) + sram combomemory sst32hf201 / sst32hf202 / sst32hf401 / sst32hf402 ?2001 silicon storage technology, inc. s71209-00-000 9/01 557 flash toggle bit (dq 6 ) during the internal program or erase operation, any con- secutive attempts to read dq 6 will produce alternating ?1?s and ?0?s, i.e., toggling between 1 and 0. when the internal program or erase operation is completed, the toggling will stop. the flash memory bank is then ready for the next operation. the toggle bit is valid after the rising edge of the fourth we# (or bef#) pulse for program operation. for sector- or bank-erase, the toggle bit is valid after the rising edge of the sixth we# (or bef#) pulse. see figure 9 for toggle bit timing diagram and figure 18 for a flowchart. flash memory da ta protection the sst32hf20x/40x flash memory bank provides both hardware and software features to protect nonvolatile data from inadvertent writes. flash hardware data protection noise/glitch protection : a we# or bef# pulse of less than 5 ns will not initiate a write cycle. v dd power up/down detection: the write operation is inhibited when v dd is less than 1.5v. write inhibit mode: forcing oe# low, bef# high, or we# high will inhibit the flash write operation. this prevents inadvertent writes during power-up or power-down. flash software data protection (sdp) the sst32hf20x/40x provide the jedec approved soft- ware data protection scheme for all flash memory bank data alteration operations, i.e., program and erase. any program operation requires the inclusion of a series of three-byte sequence. the three-byte load sequence is used to initiate the program operation, providing optimal protection from inadvertent write operations, e.g., during the system power-up or power-down. any erase operation requires the inclusion of six-byte load sequence. the sst32hf20x/40x devices are shipped with the software data protection permanently enabled. see table 4 for the specific software command codes. during sdp command sequence, invalid sdp commands will abort the device to the read mode, within read cycle time (t rc ). concurrent read and write operations the sst32hf20x/40x provide the unique benefit of being able to read from or write to sram, while simultaneously erasing or programming the flash. this allows data alter- ation code to be executed from sram, while altering the data in flash. the following table lists all valid states. the device will ignore all sdp commands when an erase or program operation is in progress. note that product identification commands use sdp; therefore, these com- mands will also be ignored while an erase or program operation is in progress. product identification the product identification mode identifies the devices as the sst32hf20x/40x and manufacturer as sst. this mode may be accessed by software operations only. the hardware device id read operation, which is typi- cally used by programmers, cannot be used on this device because of the shared lines between flash and sram in the multi-chip package. therefore, applica- tion of high voltage to pin a 9 may damage this device. users may use the software product identification opera- tion to identify the part (i.e., using the device id) when using multiple manufacturers in the same socket. for details, see tables 3 and 4 for software operation, figure 13 for the software id entry and read timing diagram, and figure 19 for the id entry command sequence flowchart. product identification mode exit/reset in order to return to the standard read mode, the software product identification mode must be exited. exiting is accomplished by issuing the exit id command sequence, which returns the device to the read operation. please note that the software-reset command is ignored during an internal program or erase operation. see table 4 for soft- ware command codes, figure 14 for timing waveform and figure 19 for a flowchart. design considerations sst recommends a high frequency 0.1 f ceramic capac- itor to be placed as close as possible between v dd and v ss , e.g., less than 1 cm away from the v dd pin of the c oncurrent r ead /w rite s tate t able flash sram program/erase read program/erase write table 1: p roduct i dentification address data manufacturer?s id 0000h 00bfh device id sst32hf201/202 0001h 2789h sst32hf401/402 0001h 2780h t1.0 557
preliminary specifications multi-purpose flash (mpf) + sram combomemory sst32hf201 / sst32hf202 / sst32hf401 / sst32hf402 5 ?2001 silicon storage technology, inc. s71209-00-000 9/01 557 device. additionally, a low frequency 4.7 f electrolytic capacitor from v dd to v ss should be placed within 1 cm of the v dd pin. figure 1: p in a ssignments for 48- ball lfbga i/o buffers 557 ill b1.0 address buffers dq 15 - dq 8 a ms -a 0 we# superflash memory sram control logic bes# bef# oe# address buffers & latches lbs# ubs# dq 7 - dq 0 f unctional b lock d iagram 557 ill f01a.0 sst32hf201/202 top view (balls facing down) 6 5 4 3 2 1 a b c d e f g h a13 a9 we# bes# a7 a3 a12 a8 nc nc nc a4 a14 a10 lbs# nc a6 a2 a15 a11 nc nc a5 a1 a16 dq7 dq5 dq2 dq0 a0 usb# dq14 dq12 dq10 dq8 bef# dq15 dq13 v dd dq11 dq9 oe# v ss dq6 dq4 dq3 dq1 v ss 557 ill f01b.0 sst32hf401/402 top view (balls facing down) 6 5 4 3 2 1 a b c d e f g h a13 a9 we# bes# a7 a3 a12 a8 nc nc a17 a4 a14 a10 lbs# nc a6 a2 a15 a11 nc nc a5 a1 a16 dq7 dq5 dq2 dq0 a0 usb# dq14 dq12 dq10 dq8 bef# dq15 dq13 v dd dq11 dq9 oe# v ss dq6 dq4 dq3 dq1 v ss
6 preliminary specifications multi-purpose flash (mpf) + sram combomemory sst32hf201 / sst32hf202 / sst32hf401 / sst32hf402 ?2001 silicon storage technology, inc. s71209-00-000 9/01 557 table 2: p in d escription symbol pin name functions a ms 1 -a 0 address inputs to provide flash addresses, a 16 -a 0 for 2m and a 17 -a 0 for 4m. to provide sram addresses, a 15 -a 0 for 1m and a 16 -a 0 for 2m. dq 15 -dq 0 data input/output to output data during read cycles and receive input data during write cycles. data is internally latched during a flash erase/program cycle. the outputs are in tri-state when oe# or bes# and bef# are high. bes# sram memory bank enable to activate the sram memory bank when bes# is low. bef# flash memory bank enable to activate the flash memory bank when bef# is low. oe# output enable to gate the data output buffers. we# write enable to control the write operations. v dd power supply 2.7-3.3v power supply v ss ground ubs# upper byte control (sram) to enable dq 15 -dq 8 lbs# lower byte control (sram) to enable dq 7 -dq 0 nc no connection unconnected pins t2.0 557 1. a ms = most significant address table 3: o peration m odes s election mode bes# 1 1. do not apply bes#=v il and bef#=v il at the same time bef# 1 oe# we# ubs# lbs# dq 15 to dq 8 dq 7 to dq 0 address not allowed v il v il x 2 2. x can be v il or v ih , but no other value. xx x x x x flash read v ih v il v il v ih xx d out d out a in program v ih v il v ih v il xx d in d in a in erase x v il v ih v il x x x x sector or block address, xxh for chip-erase sram read v il v ih v il v ih v il v il d out d out a in v il v ih v il v ih v il v ih d out high z a in v il v ih v il v ih v ih v il high z d out a in write v il v ih xv il v il v il d in d in a in v il v ih xv il v il v ih d in high z a in v il v ih xv il v ih v il high z d in a in standby v ihc v ihc x x x x high z high z x flash write inhibit x x v il xx xhigh z / d out high z / d out x xxxv ih xxhigh z / d out high z / d out x xv ih xx x xhigh z / d out high z / d out x output disable v ih v il v ih v ih x x high z high z x v il v ih xxv ih v ih high z high z x v il v ih v ih v ih x x high z high z x product identification software mode v ih v il v il v ih x x manufacturer?s id (00bfh) device id 3 3. device id for: sst32hf201/202 = 2789h and sst32hf401/402 = 2780h a msf 4 -a 1 =v il , a 0 =v ih (see table 4) 4. a ms = most significant flash address t3.2 557
preliminary specifications multi-purpose flash (mpf) + sram combomemory sst32hf201 / sst32hf202 / sst32hf401 / sst32hf402 7 ?2001 silicon storage technology, inc. s71209-00-000 9/01 557 table 4: s oftware c ommand s equence command sequence 1st bus write cycle 2nd bus write cycle 3rd bus write cycle 4th bus write cycle 5th bus write cycle 6th bus write cycle addr 1 data addr 1 data addr 1 data addr 1 data addr 1 data addr 1 data word-program 5555h aah 2aaah 55h 5555h a0h wa 2 data sector-erase 5555h aah 2aaah 55h 5555h 80h 5555h aah 2aaah 55h sa x 3 30h block-erase 5555h aah 2aaah 55h 5555h 80h 5555h aah 2aaah 55h ba x 3 50h chip-erase 5555h aah 2aaah 55h 5555h 80h 5555h aah 2aaah 55h 5555h 10h software id entry 4,5 5555h aah 2aaah 55h 5555h 90h software id exit xxh f0h software id exit 5555h aah 2aaah 55h 5555h f0h t4.1 557 1. address format a 14 -a 0 (hex),address a 15 can be v il or v ih , but no other value, for the command sequence. 2. wa = program word address 3. sa x for sector-erase; uses a ms -a 11 address lines ba x for block-erase; uses a ms -a 15 address lines a ms = most significant address a ms = a 16 for sst32hf201/202 and a 17 for sst32hf401/402 4. the device does not remain in software product id mode if powered down. 5. with a ms -a 1 = 0; sst manufacturer?s id = 00bfh, is read with a 0 = 0, sst32hf201/202 device id = 2789h, is read with a 0 = 1, sst32hf401/402 device id = 2780h, is read with a 0 = 1. absolute maximum stress ratings (applied conditions greater than those listed under ?absolute maximum stress ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. exposure to absolute maximum stress rating conditions may affect device reliability.) operating temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -20c to +85c storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65c to +125c d. c. voltage on any pin to ground potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0. 5v to v dd +0.3v transient voltage (<20 ns) on any pin to ground potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.0v to v dd +2.0v package power dissipation capability (ta = 25c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0w surface mount lead soldering temperature (3 seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240c output short circuit current 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 ma 1. outputs shorted for no more than one second. no more than one output shorted at a time. o perating r ange range ambient temp v dd commercial 0c to +70c 2.7-3.3v extended -20c to +85c 2.7-3.3v ac c onditions of t est input rise/fall time . . . . . . . . . . . . . . . 5 ns output load . . . . . . . . . . . . . . . . . . . . . c l = 30 pf see figures 15 and 16
8 preliminary specifications multi-purpose flash (mpf) + sram combomemory sst32hf201 / sst32hf202 / sst32hf401 / sst32hf402 ?2001 silicon storage technology, inc. s71209-00-000 9/01 557 table 5: dc o perating c haracteristics (v dd = v ddf and v dds = 2.7-3.3v) symbol parameter limits test conditions min max units i dd power supply current address input=v il /v ih , at f=1/t rc min, v dd =v dd max, all dqs open read flash 20 ma oe#=v il , we#=v ih bef#=v il , bes#=v ih sram 20 ma bef#=v ih , bes#=v il concurrent operation 45 ma bef#=v ih , bes#=v il write flash 25 ma we#=v il bef#=v il , bes#=v ih, oe#=v ih sram 20 ma bef#=v ih , bes#=v il i sb standby v dd current 30 a v dd =v dd max, bef#=bes#=v ihc i li input leakage current 1 a v in =gnd to v dd , v dd =v dd max i lo output leakage current 1 a v out =gnd to v dd , v dd =v dd max v il input low voltage 0.8 v v dd =v dd min v ih input high voltage 0.7 v dd vv dd =v dd max v ihc input high voltage (cmos) v dd -0.3 v v dd =v dd max v olf flash output low voltage 0.2 v i ol =100 a, v dd =v dd min v ohf flash output high voltage v dd -0.2 v i oh =-100 a, v dd =v dd min v ols output low voltage 0.4 v i ol =1 ma, v dd =v dd min v ohs output high voltage 2.2 v i oh =-500 a, v dd =v dd min t5.1 557 table 6: r ecommended s ystem p ower - up t imings symbol parameter minimum units t pu-read 1 1. this parameter is measured only for init ial qualification and after a design or proces s change that could affect this paramet er. power-up to read operation 100 s t pu-write 1 power-up to program/erase operation 100 s t6.0 557 table 7: c apacitance (ta = 25c, f=1 mhz, other pins open) parameter description test condition maximum c i/o 1 1. this parameter is measured only for init ial qualification and after a design or proces s change that could affect this paramet er. i/o pin capacitance v i/o = 0v 24 pf c in 1 input capacitance v in = 0v 12 pf t7.0 557 table 8: f lash r eliability c haracteristics symbol parameter minimum specification units test method n end 1 1. this parameter is measured only for init ial qualification and after a design or proces s change that could affect this paramet er. endurance 10,000 cycles jedec standard a117 t dr 1 data retention 100 years jedec standard a103 i lt h 1 latch up 100 + i dd ma jedec standard 78 t8.0 557
preliminary specifications multi-purpose flash (mpf) + sram combomemory sst32hf201 / sst32hf202 / sst32hf401 / sst32hf402 9 ?2001 silicon storage technology, inc. s71209-00-000 9/01 557 ac characteristics table 9: sram r ead c ycle t iming p arameters symbol parameter sst32hf201/202/401/402-70 sst32hf201/202/401/402-90 units minmaxminmax t rcs read cycle time 70 90 ns t aas address access time 70 90 ns t bes bank enable access time 70 90 ns t oes output enable access time 35 45 ns t byes ubs#, lbs# access time 70 90 ns t blzs 1 1. this parameter is measured only for init ial qualification and after a design or proces s change that could affect this paramet er. bes# to active output 0 0 ns t olzs 1 output enable to active output 0 0 ns t bylzs 1 ubs#, lbs# to active output 0 0 ns t bhzs 1 bes# to high-z output 25 35 ns t ohzs 1 output disable to high-z output 0 25 0 35 ns t byhzs 1 ubs#, lbs# to high-z output 35 45 ns t ohs output hold from address change 10 10 ns t9.0 557 table 10: sram w rite c ycle t iming p arameters symbol parameter sst32hf201/202/401/402-70 sst32hf201/202/401/402-90 units min max min max t wcs write cycle time 70 90 ns t bws bank enable to end-of-write 60 80 ns t aws address valid to end-of-write 60 80 ns t asts address set-up time 0 0 ns t wps write pulse width 60 80 ns t wrs write recovery time 0 0 ns t byws ubs#, lbs# to end-of-write 60 80 ns t odws output disable from we# low 30 40 ns t oews output enable from we# high 0 0 ns t dss data set-up time 30 40 ns t dhs data hold from write time 0 0 ns t10.0 557
10 preliminary specifications multi-purpose flash (mpf) + sram combomemory sst32hf201 / sst32hf202 / sst32hf401 / sst32hf402 ?2001 silicon storage technology, inc. s71209-00-000 9/01 557 table 11: f lash r ead c ycle t iming p arameters symbol parameter sst32hf201/202/401/402-70 sst32hf201/202/401/402-90 units min max min max t rc read cycle time 70 90 ns t be bank enable access time 70 90 ns t aa address access time 70 90 ns t oe output enable access time 35 45 ns t blz 1 bef# low to active output 0 0 ns t olz 1 oe# low to active output 0 0 ns t bhz 1 bef# high to high-z output 20 30 ns t ohz 1 oe# high to high-z output 20 30 ns t oh 1 output hold from address change 0 0 ns t11.0 557 1. this parameter is measured only for init ial qualification and after a design or proces s change that could affect this paramet er. table 12: f lash p rogram /e rase c ycle t iming p arameters symbol parameter min max units t bp word-program time 20 s t as address setup time 0 ns t ah address hold time 30 ns t bs we# and bef# setup time 0 ns t bh we# and bef# hold time 0 ns t oes oe# high setup time 0 ns t oeh oe# high hold time 10 ns t bpw bef# pulse width 40 ns t wp we# pulse width 40 ns t wph we# pulse width high 30 ns t bph bef# pulse width high 30 ns t ds data setup time 30 ns t dh data hold time 0 ns t ida software id access and exit time 150 ns t se sector-erase 25 ms t be block-erase 25 ms t sce chip-erase 100 ms t12.0 557
preliminary specifications multi-purpose flash (mpf) + sram combomemory sst32hf201 / sst32hf202 / sst32hf401 / sst32hf402 11 ?2001 silicon storage technology, inc. s71209-00-000 9/01 557 figure 2: sram r ead c ycle t iming d iagram figure 3: sram w rite c ycle t iming d iagram (we# c ontrolled ) 1 addresses a mss-0 dq 15-0 ubs#, lbs# note: we# remains high (v ih ) for the read cycle a mss = most significant sram address oe# bes# t rcs t aas t bes t oes t blzs t olzs t byes t bylzs t byhzs data valid t ohzs t bhzs t ohs 557 ill f02.0 t aws addresses a mss-0 bes# we# ubs#, lbs# notes: 1. if oe# is high during the write cycle, the outputs will remain at high impedance. 2. if bes# goes low coincident with or after we# goes low, the output will remain at high impedance. if bes# goes high coincident with or before we# goes high, the output will remain at high impedance. because d in signals may be in the output state at this time, input signals of reverse polarity must not be applied. t wps t wrs t wcs t asts t bws t byws t odws t oews t dss t dhs 557 ill f03.1 note 2 note 2 dq 15-8, dq 7-0 valid data in
12 preliminary specifications multi-purpose flash (mpf) + sram combomemory sst32hf201 / sst32hf202 / sst32hf401 / sst32hf402 ?2001 silicon storage technology, inc. s71209-00-000 9/01 557 figure 4: sram w rite c ycle t iming d iagram (ubs#, lbs# c ontrolled ) 1 figure 5: f lash r ead c ycle t iming d iagram addresses a mss-0 we# bes# t bws t aws t wcs t wps t wrs t asts t byws dq 15-8, dq 7-0 valid data in note 2 note 2 t dss t dhs ubs#, lbs# notes: 1. if oe# is high during the write cycle, the outputs will remain at high impedance. 2. because d in signals may be in the output state at this time, input signals of reverse polarity must not be applied. 557 ill f04.0 557 ill f05.0 addresses a msf-0 dq 15-0 we# oe# bef# t be t rc t aa t oe t olz v ih high-z t blz t oh t bhz high-z data valid data valid t ohz a msf = most significant flash address
preliminary specifications multi-purpose flash (mpf) + sram combomemory sst32hf201 / sst32hf202 / sst32hf401 / sst32hf402 13 ?2001 silicon storage technology, inc. s71209-00-000 9/01 557 figure 6: f lash we# c ontrolled p rogram c ycle t iming d iagram figure 7: bef# c ontrolled f lash p rogram c ycle t iming d iagram 557 ill f06.0 addresses a msf-0 dq 15-0 t dh t wph t ds t wp t ah t as t ch t cs bef# sw0 sw1 sw2 5555 2aaa 5555 addr xxaa xx55 xxa0 data internal program operation starts word (addr/data) oe# we# t bp a msf = most significant flash address note: x can be v il or v ih , but no other value 557 ill f07.0 addresses a msf-0 dq 15-0 t dh t cph t ds t cp t ah t as t ch t cs we# sw0 sw1 sw2 5555 2aaa 5555 addr xxaa xx55 xxa0 data internal program operation starts word (addr/data) oe# bef# t bp a msf = most significant flash address note: x can be v il or v ih , but no other value
14 preliminary specifications multi-purpose flash (mpf) + sram combomemory sst32hf201 / sst32hf202 / sst32hf401 / sst32hf402 ?2001 silicon storage technology, inc. s71209-00-000 9/01 557 figure 8: f lash d ata # p olling t iming d iagram figure 9: f lash t oggle b it t iming d iagram 557 ill f08.0 addresses a msf-0 dq 7 data data# data# data we# oe# bef# t oeh t oe t ce t oes a msf = most significant flash address 557 ill f09.0 addresses a msf-0 dq 6 we# oe# bef# t oe t oeh t be t oes two read cycles with same outputs a msf = most significant flash address
preliminary specifications multi-purpose flash (mpf) + sram combomemory sst32hf201 / sst32hf202 / sst32hf401 / sst32hf402 15 ?2001 silicon storage technology, inc. s71209-00-000 9/01 557 figure 10: we# c ontrolled f lash c hip -e rase t iming d iagram figure 11: we# c ontrolled f lash s ector -e rase t iming d iagram 557 ill f10.0 address a msf-0 dq 15-0 we# sw0 sw1 sw2 sw3 sw4 sw5 5555 2aaa 2aaa 5555 5555 xx55 xx10 xx55 xxaa xx80 xxaa 5555 oe# ce# six-byte code for chip-erase t sce t wp note: this device also supports ce# controlled chip-erase operation. the we# and ce# signals are interchageable as long as minimum timings are met. (see table 12) x can be v il or v ih , but no other value a msf = most significant flash address 557 ill f11.0 addresses a msf-0 dq 15-0 we# sw0 note: the device also supports bef# controlled sector-erase operation. the we# and bef# signals are interchangeable as long as minimum timings are met. (see table 12) x can be v il or v ih , but no other value sa x = sector address a msf = most significant flash address sw1 sw2 sw3 sw4 sw5 5555 2aaa 2aaa 5555 5555 xx55 xx30 xx55 xxaa xx80 xxaa sa x oe# bef# six-word code for sector-erase t se t wp
16 preliminary specifications multi-purpose flash (mpf) + sram combomemory sst32hf201 / sst32hf202 / sst32hf401 / sst32hf402 ?2001 silicon storage technology, inc. s71209-00-000 9/01 557 figure 12: we# c ontrolled f lash b lock -e rase t iming d iagram figure 13: s oftware id e ntry and r ead 557 ill f12.0 addresses a msf-0 dq 15-0 we# sw0 sw1 sw2 sw3 sw4 sw5 5555 2aaa 2aaa 5555 5555 xx55 xx50 xx55 xxaa xx80 xxaa ba x oe# bef# six-word code for block-erase t sbe t wp note: the device also supports bef# controlled block-erase operation. the we# and bef# signals are interchangeable as long as minimum timings are met. (see table 12) x can be v il or v ih , but no other value ba x = block address a msf = most significant flash address 557 ill f13.0 address a 14-0 t ida dq 15-0 we# sw0 sw1 sw2 mfg id 5555 2aaa 5555 0000 0001 oe# bef# three-word sequence for software id entry t wp t wph t aa 00bf device id xx55 xxaa xx90 note: x can be v il or v ih , but no other value device id = 2789h for sst32vf201/202 and 2780h for sst32vf401/402
preliminary specifications multi-purpose flash (mpf) + sram combomemory sst32hf201 / sst32hf202 / sst32hf401 / sst32hf402 17 ?2001 silicon storage technology, inc. s71209-00-000 9/01 557 figure 14: s oftware id e xit and r eset 557 ill f14.0 address a 14-0 dq 15-0 t ida t wp t whp we# sw0 sw1 sw2 5555 2aaa 5555 three-word sequence for software id exit and reset oe# bef# xxaa xx55 xxf0 note: x can be v il or v ih , but no other value
18 preliminary specifications multi-purpose flash (mpf) + sram combomemory sst32hf201 / sst32hf202 / sst32hf401 / sst32hf402 ?2001 silicon storage technology, inc. s71209-00-000 9/01 557 figure 15: ac i nput /o utput r eference w aveforms figure 16: a t est l oad e xample 557 ill f15.0 reference points output input v it v iht v ilt v ot ac test inputs are driven at v iht (0.9 v dd ) for a logic ?1? and v ilt (0.1 v dd ) for a logic ?0?. measurement reference points for inputs and outputs are v it (0.5 v dd ) and v ot (0.5 v dd ). input rise and fall times (10% ? 90%) are <5 ns. note: v it - v input te s t v ot - v output te s t v iht - v input high test v ilt - v input low test 557 ill f16.0 to tester to dut c l
preliminary specifications multi-purpose flash (mpf) + sram combomemory sst32hf201 / sst32hf202 / sst32hf401 / sst32hf402 19 ?2001 silicon storage technology, inc. s71209-00-000 9/01 557 figure 17: w ord -p rogram a lgorithm 557 ill f17.0 start write data: xxaah address: 5555h write data: xx55h address: 2aaah write data: xxa0h address: 5555h write word address/word data wait for end of program (t bp , data# polling bit, or toggle bit operation) program completed x can be v il or v ih , but no other value.
20 preliminary specifications multi-purpose flash (mpf) + sram combomemory sst32hf201 / sst32hf202 / sst32hf401 / sst32hf402 ?2001 silicon storage technology, inc. s71209-00-000 9/01 557 figure 18: w ait o ptions 557 ill f18.0 wait t bp , t sce, or t be program/erase initiated internal timer toggle bit ye s ye s no no program/erase completed does dq 6 match? read same word data# polling program/erase completed program/erase completed read word is dq 7 = true data? read dq 7 program/erase initiated program/erase initiated
preliminary specifications multi-purpose flash (mpf) + sram combomemory sst32hf201 / sst32hf202 / sst32hf401 / sst32hf402 21 ?2001 silicon storage technology, inc. s71209-00-000 9/01 557 figure 19: s oftware p roduct c ommand f lowcharts 557 ill f19.0 write data: xxaah address: 5555h software product id entry command sequence write data: xx55h address: 2aaah write data: xx90h address: 5555h wait t ida read software id write data: xxaah address: 5555h software product id exit & reset command sequence write data: xx55h address: 2aaah write data: xxf0h address: 5555h write data: xxf0h address: xxxxh return to normal operation wait t ida wait t ida return to normal operation x can be v il or v ih , but no other value.
22 preliminary specifications multi-purpose flash (mpf) + sram combomemory sst32hf201 / sst32hf202 / sst32hf401 / sst32hf402 ?2001 silicon storage technology, inc. s71209-00-000 9/01 557 figure 20: e rase c ommand s equence 557 ill f20.0 load data: xxaah address: 5555h chip-erase command sequence load data: xx55h address: 2aaah load data: xx80h address: 5555h load data: xx55h address: 2aaah load data: xx10h address: 5555h load data: xxaah address: 5555h wait t sce chip erased to ffffh load data: xxaah address: 5555h sector-erase command sequence load data: xx55h address: 2aaah load data: xx80h address: 5555h load data: xx55h address: 2aaah load data: xx30h address: sa x load data: xxaah address: 5555h wait t se sector erased to ffffh load data: xxaah address: 5555h block-erase command sequence load data: xx55h address: 2aaah load data: xx80h address: 5555h load data: xx55h address: 2aaah load data: xx50h address: ba x load data: xxaah address: 5555h wait t be block erased to ffffh x can be v il or v ih , but no other value.
preliminary specifications multi-purpose flash (mpf) + sram combomemory sst32hf201 / sst32hf202 / sst32hf401 / sst32hf402 23 ?2001 silicon storage technology, inc. s71209-00-000 9/01 557 figure 21: c oncurrent o peration f lowchart 557 ill f21.0 load sdp command sequence concurrent operation flash program/erase initiated wait for end of write indication flash operation completed end concurrent operation read or write sram end wait
24 preliminary specifications multi-purpose flash (mpf) + sram combomemory sst32hf201 / sst32hf202 / sst32hf401 / sst32hf402 ?2001 silicon storage technology, inc. s71209-00-000 9/01 557 product ordering information device speed suffix1 suffix2 sst32 h fxxx -xxx -x x -x x package modifier k = 48 balls package type l3 = lfbga (6mm x 8mm x 1.4mm) temperature range c = commercial = 0c to +70c e = extended = -20c to +85c minimum endurance 4 = 10,000 cycles read access speed 70 = 70 ns 90 = 90 ns density 201 = 2 mbit flash + 1 mbit sram 202 = 2 mbit flash + 2 mbit sram 401 = 4 mbit flash + 1 mbit sram 402 = 4 mbit flash + 2 mbit sram voltage h = 2.7-3.3v device family 32 = mpf + sram combomemory
preliminary specifications multi-purpose flash (mpf) + sram combomemory sst32hf201 / sst32hf202 / sst32hf401 / sst32hf402 25 ?2001 silicon storage technology, inc. s71209-00-000 9/01 557 valid combinations for sst32hf201 SST32HF201-70-4C-L3K sst32hf201-70-4e-l3k sst32hf201-90-4c-l3k sst32hf201-90-4e-l3k valid combinations for sst32hf202 sst32hf202-70-4c-l3k sst32hf202-70-4e-l3k sst32hf202-90-4c-l3k sst32hf202-90-4e-l3k valid combinations for sst32hf401 sst32hf401-70-4c-l3k sst32hf401-70-4e-l3k sst32hf401-90-4c-l3k sst32hf401-90-4e-l3k valid combinations for sst32hf402 sst32hf402-70-4c-l3k sst32hf402-70-4e-l3k sst32hf402-90-4c-l3k sst32hf402-90-4e-l3k note: valid combinations are those products in mass produc tion or will be in mass production. consult your sst sales representative to confirm availability of valid combinations and to determine availability of new combinations.
26 preliminary specifications multi-purpose flash (mpf) + sram combomemory sst32hf201 / sst32hf202 / sst32hf401 / sst32hf402 ?2001 silicon storage technology, inc. s71209-00-000 9/01 557 packaging diagrams 48- ball l ow - profile , f ine - pitch b all g rid a rray (lfbga) 6 mm x 8 mm sst p ackage c ode : l3k a1 corner h g f e d c b a a b c d e f g h bottom view top view side view 6 5 4 3 2 1 6 5 4 3 2 1 seating plane 0.35 0.05 1.30 0.10 0.15 6.00 0.20 0.45 0.05 (48x) a1 corner 8.00 0.20 0.80 4.00 0.80 5.60 48ba-lfbga-l3k-6x8-450mic-ill.1 note: 1. although many dimensions are similar to those of jedec publication 95, mo-210, this specific package is not registered. 2. all linear dimensions are in millimeters. 3. coplanarity: 0.1 (.05) mm. 4. the actual shape of the corners may be slightly different than as portrayed in the drawing. 1mm silicon storage technology, inc. 1171 sonora court sunnyvale, ca 94086 telephone 408-735-9110 fax 408-735-9036 www.superflash.com or www.ssti.com

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